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SC624A
LED Light Management Unit
POWER MANAGEMENT Features
Input supply voltage range -- 3.0V to 5.5V Charge pump modes -- 1x, 1.5x and 2x Four programmable current sinks with 32 steps from 0.5mA to 25mA Two user-configurable 100mA low-noise LDO regulators Charge pump frequency -- 250kHz I2C compatible interface -- up to 400kHz Backlight current accuracy 1.5% typical Backlight current matching 0.5% typical Programmable fade-in/fade-out for main backlight Automatic sleep mode (LEDs off ) -- IQ = 100A Low shutdown current -- 0.1A (typical) Ultra-thin package -- 3mm x 3mm x 0.6mm Fully WEEE and RoHS compliant
Charge Pump, 4 LEDs, Dual LDOs, and I2C Interface Description
The SC624A is a high efficiency charge pump LED driver using Semtech's proprietary mAhXLifeTM technology. Performance is optimized for use in single-cell Li-ion battery applications. The charge pump provides backlight current in conjunction with four matched current sinks. The load and supply conditions determine whether the charge pump operates in 1x, 1.5x, or 2x mode. An optional fading feature that gradually adjusts the backlight current is provided to simplify control software. The SC624A also provides two low-dropout, low-noise linear regulators for powering a camera module or other peripheral circuits. The SC624A uses an I2C compatible serial interface. The interface controls all functions of the device, including backlight current and two LDO voltage outputs. In sleep mode, the device reduces quiescent current to 100A while continuing to monitor the serial interface. The two LDOs can be enabled when the device is in sleep mode. Total current reduces to 0.1A in shutdown.
Applications
Cellular phone backlighting PDA backlighting Camera I/O and core power
Typical Application Circuit
MAIN BACKLIGHT VBAT CIN 1F VIN I2C Data I2C Clock SDA SCL EN BYP CBYP 22nF AGND PGND C1+ C1 1F C1BL 1 BL 2 BL 3 BL 4 LDO 1 LDO 2 C2+ C2C2 1F CLDO1 1F VLDO1 = 2.5V to 3.3V VLDO2 = 1.5V to 1.8V CLDO2 1F VOUT
SC624A
COUT 2.2F
Enable Control
US Patents: 6,504,422; 6,794,926 June 27, 2007 (c) 2007 Semtech Corporation 1
SC624A
Pin Configuration Ordering Information
Device
C1+ C2+ C1VIN VOUT
Package
MLPQ-UT-20 3x3 Evaluation Board
SC624AULTRT(1)(2) SC624AEVB
20 C2PGND NC BL1 BL2 1 2 3 4 5 6
19
18
17
16 15 LDO1 LDO2 BYP EN SDA
TOP VIEW
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant.
14 13 12
T
11 9 10
7
8
AGND
SCL
BL3
MLPQ-UT-20; 3x3, 20 LEAD JA = 35C/W
Marking Information
yyww = Date Code xxxx = Semtech Lot No.
BL4
624A yyww xxxx
NC
2
SC624A
Absolute Maximum Ratings
VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 VOUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 C1+, C2+ (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VOUT + 0.3) Pin Voltage -- All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3) VOUT Short Circuit Duration . . . . . . . . . . . . . . . . Continuous VLDO1, VLDO2 Short Circuit Duration. . . . . . . Continuous ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Recommended Operating Conditions
Ambient Temperature Range (C) . . . . . . . . -40 < TA < +85 VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 < VIN < 5.5 VOUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 < VOUT < 5.25 Voltage Difference between any two LEDs (V) . . . . . . < 1.2
Thermal Information
Thermal Resistance, Junction to Ambient(2) (C/W) . . . . 35 Maximum Junction Temperature (C) . . . . . . . . . . . . . . +150 Storage Temperature Range (C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (C) . . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless otherwise noted, TA = +25C for Typ, -40C to +85C for Min and Max, TJ(MAX) = 125C, VIN = 3.0V to 4.2V, CIN= C1= C2= 2.2F, COUT = 4.7F (ESR = 0.03), VF 1.2V(1)
Parameter
Supply Specifications Shutdown Current
Symbol
Conditions
Min
Typ
Max
Units
IQ(OFF)
Shutdown, VIN = 4.2V Sleep (LDOs off ), EN = VIN Sleep (LDOs on), EN = VIN, VIN > (VLDO + 300mV), ILDO < 200mA
0.1 100 220 3.8 4.6 4.6
2 160
A
A 340 4.65 5.85 5.85 mA
Total Quiescent Current
IQ
Charge pump in 1x mode, 4 backlights on Charge pump in 1.5x mode, 4 backlights on Charge pump in 2x mode, 4 backlights on
Fault Protection Output Short Circuit Current Limit Over-Temperature IOUT(SC) TOTP VOUT pin shorted to GND 300 160 mA C
3
SC624A
Electrical Characteristics (continued)
Parameter
Fault Protection (continued) Charge Pump Over-Voltage Protection VOVP VUVLO Undervoltage Lockout VUVLO-HYS Charge Pump Electrical Specifications Maximum Total Output Current Backlight Current Setting Backlight Current Accuracy Backlight Current Matching 1x Mode to 1.5x Mode Falling Transition Voltage 1.5x Mode to 1x Mode Hysteresis 1.5x Mode to 2x Mode Falling Transition Voltage 2x Mode to 1.5x Mode Hysteresis Current Sink Off-State Leakage Current Pump Frequency LDO Electrical Specifications LDO1 Voltage Setting VLDO1 VLDO2 VLDO1, VLDO2 Range of nominal settings in 100mV increments Range of nominal settings in 100mV increments VIN = 3.7V, ILDO = 1mA LDO1, ILDO1 = 1mA, VOUT = 2.8V Line Regulation VLINE LDO2, ILDO2 = 1mA, VOUT = 1.8V 1.3 4.8 2.5 3.3 V IOUT(MAX) IBL IBL_ACC IBL-BL V TRANS1x VHYST1x V TRANS1.5x VHYST1.5x IBLn fPUMP VIN > 3.4V, sum of all active LED currents, VOUT(MAX) = 4.2V Nominal setting for BL1 thru BL4 VIN = 3.7V, IBL = 12mA, TA = 25C VIN = 3.7V, IBL = 12mA(2) IOUT = 40mA, IBLn = 10mA, VOUT = 3.2V IOUT = 40mA, IBLn = 10mA, VOUT = 3.2V IOUT = 40mA, IBLn = 10mA, VOUT = 4.0V(3) IOUT = 40mA, IBLn = 10mA, VOUT = 4.0V(3) VIN = VBLn = 4.2V VIN = 3.2V 100 0.5 -8 -3.5 1.5 0.5 3.27 25 +8 +3.5 mA mA % % V 300 mV VOUT pin open circuit, VOUT = VOVP rising threshold Decreasing VIN 5.3 5.7 2.4 6.0 V V
Symbol
Conditions
Min
Typ
Max
Units
250
mV
2.92
V
300
mV
0.1 250
1
A kHz
LDO2 Voltage Setting LDO1, LDO2 Output Voltage Accuracy
1.5
1.8
V
-3.5
3
+3.5
%
2.1
7.2 mV
4
SC624A
Electrical Characteristics (continued)
Parameter Symbol Conditions Min Typ Max Units
LDO Electrical Specifications (continued) VLDO1 = 3.3V, VIN = 3.7V, ILDO1 = 1mA to 100 mA VLDO2 = 1.8V, VIN = 3.7V, ILDO2 = 1mA to 100 mA ILDO1 = 100mA 200 2.5V < VLDO1 < 3V, f < 1kHz, CBYP = 22nF, ILDO1 = 50mA, VIN = 3.7V with 0.5VP-P ripple f < 1kHz, CBYP = 22nF, ILDO2 = 50mA, VIN = 3.7V with 0.5VP-P ripple LDO1, 10Hz < f < 100kHz, CBYP = 22nF, CLDO = 1F, ILDO1 = 50 mA, VIN = 3.7V, 2.5V < VLDO1 < 3V LDO2, 10Hz < f < 100kHz, CBYP = 22nF, CLDO = 1F, ILDO2 = 50 mA, VIN = 3.7V 50 dB 60 100 25 mV 20 150 mV mA
Load Regulation
VLOAD
Dropout Voltage(4) Current Limit
VD ILIM PSRRLDO1 PSRRLDO2 en-LDO1
Power Supply Rejection Ratio
100 VRMS 50 1 F
Output Voltage Noise en-LDO2 Minimum Output Capacitor CLDO(MIN)
Digital I/O Electrical Specifications (EN) Input High Threshold Input Low Threshold Input High Current Input Low Current VIH VIL IIH IIL VIN = 5.5V VIN = 3.0V VIN = 5.5V VIN = 5.5V -1 -1 1.6 0.4 +1 +1 V V A A
I2C Interface
Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January, 2000. VB-IL Digital Input Voltage VB-IH SDA Output Low Level Digital Input Current Hysteresis of Schmitt Trigger Inputs Maximum Glitch Pulse Rejection IB-IN VHYS tSP IDIN (SDA) 3mA -0.2 0.1 1.6 0.4 0.2 V V A V 0.4 V
50
ns
5
SC624A
Electrical Characteristics (continued)
Parameter
I2C Interface (Continued) I/O Pin Capacitance I2C Timing Clock Frequency SCL Low Period(5) SCL High Period(5) Data Hold Time(5) Data Setup Time(5) Setup Time for Repeated START Condition(5) Hold Time for Repeated START Condition(5) Setup Time for STOP Condition(5) Bus-Free Time Between STOP and START(5) Interface Start-up Time(5) fSCL tLOW tHIGH tHD_DAT tSU_DAT tSU_STA tHD_STA tSU_STO tBUF tEN Bus Start-up Time After EN Pin is Pulled High 1.3 0.6 0 100 0.6 400 440 kHz s s s s s CIN 10 pF
Symbol
Conditions
Min
Typ
Max
Units
0.6
s
0.6
s
1.3
s
1
ms
Notes: (1) VF is the voltage difference between any two LEDs. (2) Current matching equals [IBL(MAX) - IBL(MIN] / [IBL(MAX) + IBL(MIN)]. (3) Test voltage is VOUT = 4.0V -- a relatively extreme LED voltage -- to force a transition during test. Typically VOUT = 3.2V for white LEDs. (4) Dropout is defined as (VIN - VLDO1) when VLDO1 drops 100mV from nominal. Dropout does not apply to LDO2 since it has a maximum output voltage of 1.8V. (5) Guaranteed by design
6
SC624A
Typical Characteristics
Battery Current (4 LEDs) -- 25mA Each
160 VOUT=3.66V, IOUT=100mA, 25C
Battery Current (4 LEDs) -- 12mA Each
80 VOUT=3.50V, IOUT=48mA, 25C
150
73
Battery Current (mA)
Battery Current (mA)
140
66
130
59
120
110
52
100 4.2
4.0
3.8
3.6 VIN (V)
3.4
3.2
3.0
45 4.2
4.0
3.8
3.6 VIN (V)
3.4
3.2
3.0
Backlight Efficiency (4 LEDs) -- 25mA Each
100 VOUT=3.66V, IOUT=100mA, 25C
Backlight Efficiency (4 LEDs) -- 12mA Each
100 VOUT=3.50V, IOUT=48mA, 25C
90
90
% Efficiency
% Efficiency
80
80
70
70
60
60
50 4.2
4.0
3.8
3.6 VIN (V)
3.4
3.2
3.0
50 4.2
4.0
3.8
3.6 VIN (V)
3.4
3.2
3.0
Battery Current (4 LEDs) -- 5.0mA Each
40 VOUT=3.33V, IOUT=20mA, 25C
100
Backlight Efficiency (4 LEDs) -- 5.0mA Each
VOUT=3.33V, IOUT=20mA, 25C
35
90
Battery Current (mA)
% Efficiency
4.0 3.8 3.6 VIN (V) 3.4 3.2 3.0
30
80
25
70
20
60
15 4.2
50 4.2
4.0
3.8
3.6 VIN (V)
3.4
3.2
3.0
7
SC624A
Typical Characteristics (continued)
PSRR vs. Frequency (LDO1)
0 -10 -20
PSRR (dB)
PSRR vs. Frequency (LDO2)
0 -10 -20
PSRR (dB)
VIN=3.7V at 25C, ILDO1=50mA, VLDO1=2.8V
VIN=3.7V at 25C, ILDO2=50mA, VLDO2=1.8V
-30 -40 -50 -60 -70 10 100 Frequency (Hz) 1000 10000
-30 -40 -50 -60 -70 10
100
Frequency (Hz)
1000
10000
Noise vs Load Current (LDO1)
100 VLDO1=2.8V, VIN=3.7V, 25C 100
Noise vs Load Current (LDO2)
VLDO2=1.8V, VIN=3.7V, 25C
90
80
Noise (V)
Noise (V)
80
60
70
40
60
20
50
0 0 20 40 ILDO1 (mA) 60 80 100
0
20
40 ILDO2 (mA)
60
80
100
8
SC624A
Typical Characteristics (continued)
Load Regulation (LDO1)
24 VLDO1=3.3V, VIN=3.7V, 25C
Load Regulation (LDO2)
24 VLDO2=1.8V, VIN=3.7V, 25C
16
Output Voltage Variation (mV)
16
Output Voltage Variation (mV)
8
8
0
0
-8
-8
-16 -24 0 30 60 ILDO1(mA) 90 120 150
-16 -24 0 30 60 ILDO2(mA) 90 120 150
Line Regulation (LDO1)
2 VLDO1=2.8V, ILDO1=1mA, 25C
2
Line Regulation (LDO2)
VLDO2=1.8V, ILDO2=1mA, 25C
Output Voltage Variation (mV)
0
Output Voltage Variation (mV)
1
1
0
-1
-1
-2
-2
-3 4.2
4.0
3.8
3.6 VIN (V)
3.4
3.2
3.0
-3 4.2 4.0 3.8 3.6 VIN (V) 3.4 3.2 3.0
9
SC624A
Typical Characteristics (continued)
Load Transient Response (LDO1) -- Rising Edge
VIN=3.7V, VLDO1=2.8V, ILDO1=1 to 100mA VLDO1 (50mV/div) VLDO2 (50mV/div)
Load Transient Response (LDO2) -- Rising Edge
VIN=3.7V, VLDO2=1.8V, ILDO2=1 to 100mA
ILDO1 (100mA/div) Time (20s/div)
ILDO2 (100mA/div) Time (20s/div)
Load Transient Response (LDO1) -- Falling Edge
VIN=3.7V, VLDO1=2.8V, ILDO1=100 to 1mA
Load Transient Response (LDO2) -- Falling Edge
VIN=3.7V, VLDO2=1.8V, ILDO2=100 to 1mA
VLDO1 (50mV/div) VLDO2 (50mV/div)
ILDO1 (100mA/div) ILDO2 (100mA/div)
Time (200s/div)
Time (200s/div)
Output Short Circuit Current Limit
VOUT=0V, VIN=4.2V, 25C VBL1 (500mV/div) VOUT (1V/div) VOUT (2V/div)
Output Open Circuit Protection
VIN=3.7V, 25C
IOUT (100mA/div)
IBL1 (20mA/div)
Time (1ms/div)
Time (200s/div)
10
SC624A
Pin Descriptions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T
Pin Name
C2PGND NC BL1 BL2 BL3 BL4 AGND SCL NC SDA EN BYP LDO2 LDO1 VOUT C2+ C1+ VIN C1THERMAL PAD
Pin Function
Negative connection to bucket capacitor 2 -- requires a 1F capacitor connected to C2+ Ground pin for high current charge pump Unused pin -- do not terminate Current sink output for main backlight LED 1 -- leave this pin open if unused Current sink output for main backlight LED 2 -- leave this pin open if unused Current sink output for main backlight LED 3 -- leave this pin open if unused Current sink output for main backlight LED 4 -- leave this pin open if unused Analog ground pin -- connect to ground and separate from PGND current I2C clock input pin Unused pin -- do not terminate I2C bi-directional data pin -- used for read and write operations for all internal registers (refer to Register Map and I2C Interface sections) Chip enable -- active high -- low state resets all registers (see register map table) Bypass pin for voltage reference -- connect with a 22nF capacitor to AGND Output of LDO2 -- connect with a 1F capacitor to AGND Output of LDO1 -- connect with a 1F capacitor to AGND Charge pump output -- all LED anode pins should be connected to this pin -- requires a 2.2F capacitor to PGND Positive connection to bucket capacitor 2 -- requires a 1F capacitor connected to C2Positive connection to bucket capacitor 1 -- requires a 1F capacitor connected to C1Battery voltage input -- connect with a 1F capacitor to PGND Negative connection to bucket capacitor 1 -- requires a 1F capacitor connected to C1+ Thermal pad for heatsinking purposes -- connect to ground plane using multiple vias -- not connected internally
11
SC624A
Block Diagram
C1+ 18
C120
C2+ 17
C21 VOUT
VIN
19
VIN
mAhXLifeTM Fractional Charge Pump (1x, 1.5x, 2x)
16 2
VOUT PGND
EN SDA
12 11 I2 C Compatible Interface and Logic Control Oscillator 4 5 6 Current Setting DAC 7 BL1 BL2 BL3 BL4
SCL
9
BYP
13
Bandgap Reference
3 Voltage Setting DAC
NC
VIN
LDO1 NC 10 VIN
15
LDO1
LDO2 AGND 8
14
LDO2
12
SC624A
Applications Information
General Description
This design is optimized for handheld applications supplied from a single Li-Ion cell and includes the following key features: the typical application circuit diagram. These capacitors should be equal in value, with a minimum capacitance of 1F to support the charge pump current requirements. The device also requires a 1F capacitor on the VIN pin and a 2.2F capacitor on the VOUT pin to minimize noise and support the output drive requirements. Capacitors with X7R or X5R ceramic dielectric are strongly recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application.
* * * *
A high efficiency fractional charge pump that supplies power to all LEDs Four matched current sinks that control LED backlighting current, with 0.5mA to 25mA per LED Two adjustable LDOs with outputs ranging from 2.5V to 3.3V for LDO1 and 1.5V to 1.8V for LDO2, adjustable in 100mV increments An I2C compatible interface that provides control of all device functions
LED Backlight Current Sinks
The backlight current is set via the I2C compatible interface. The current is regulated to one of 32 values between 0.5mA and 25mA. The step size varies depending upon the current setting. Between 0.5mA and 12mA, the step size is 0.5mA. The step size increases to 1mA for settings between 12mA and 15mA and 2mA for settings greater than 15mA. This feature allows finer adjustment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in LED brightness. All backlight current sinks have matched currents, even when there is variation in the forward voltages (VF ) of the LEDs. A VF of 1.2V is supported when the input voltage is at 3.0V. Higher VF LED mis-match is supported when VIN is higher than 3.0V. All current sink outputs are compared and the lowest output is used for setting the voltage regulation at the VOUT pin. This is done to ensure that sufficient bias exists for all LEDs. The backlight LEDs default to the off state upon powerup. For backlight applications using less than four LEDs, any unused output must be left open and the unused LED driver must remain disabled. When writing to the Backlight Enable Control register, a zero (0) must be written to the corresponding bit of any unused output.
High Current Fractional Charge Pump
The backlight outputs are supported by a high efficiency, high current fractional charge pump output at the VOUT pin. The charge pump multiplies the input voltage by 1, 1.5, or 2 times. The charge pump switches at a fixed frequency of 250kHz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve efficiency. The mode selection circuit automatically selects the 1x, 1.5x or 2x mode based on circuit conditions. Circuit conditions such as low input voltage, high output current, or high LED voltage place a higher demand on the charge pump output. A higher numerical mode may be needed momentarily to maintain regulation at the VOUT pin during intervals of high demand, such as the droop at the VIN pin during a supply voltage transient. The charge pump responds to these momentary high demands, setting the charge pump to the optimum mode (1x, 1.5x or 2x), as needed to deliver the output voltage and load current while optimizing efficiency. Hysteresis is provided to prevent mode toggling. The charge pump requires two bucket capacitors for low ripple operation. One capacitor must be connected between the C1+ and C1- pins and the other must be connected between the C2+ and C2- pins as shown in
13
SC624A
Applications Information (continued)
Backlight Quiescent Current
The quiescent current required to operate all four backlights is reduced by 1.5mA when backlight current is set to 4.0mA or less. This feature results in higher efficiency under light-load conditions. Further reduction in quiescent current will result from using fewer than four LEDs.
Sleep Mode
When all LEDs are off, sleep mode is activated. This is a reduced current mode that helps minimize overall current consumption by turning off the clock and the charge pump while continuing to monitor the serial interface for commands. Both LDOs can be powered up while in sleep mode.
Fade-In and Fade-Out
Backlight brightness can be set to automatically fade-in when current is set to increase and fade-out when current is set to decrease. When enabled with a new current setting, the current will step through each incremental setting between the old and new values. The result is a visually smooth change in brightness with a rate of fade that can be set to 8, 16, 24, or 32 ms per step.
I2C Compatible Interface Functions
All device functions can be controlled via the I2C compatible interface. The interface is described in detail in the Serial Interface section of the datasheet.
Protection Features
The SC624A provides several protection features to safeguard the device from catastrophic failures. These features include:
Programmable LDO Outputs
Two low dropout (LDO) regulators are provided for camera module I/O and core power. Each LDO has at least 100mA of available load current with 3.5% accuracy. The minimum current limit is 200mA, so outputs greater than 100mA are possible at somewhat reduced accuracy. A 1F, low ESR capacitor should be used as a bypass capacitor on each LDO output to reduce noise and ensure stability. In addition, it is recommended that a minimum 22nF capacitor be connected from the BYP pin to ground to minimize noise and achieve optimum power supply rejection. A larger capacitor can be used for this function, but at the expense of increasing turnon time. Capacitors with X7R or X5R ceramic dielectric are strongly recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application.
* * * * *
Output Open Circuit Protection Over-Temperature Protection Charge Pump Output Current Limit LDO Current Limit LED Float Detection
Output Open Circuit Protection Over-Voltage Protection (OVP) is provided at the VOUT pin to prevent the charge pump from producing an excessively high output voltage. In the event of an open circuit at VOUT, the charge pump runs in open loop and the voltage rises up to the OVP limit. OVP operation is hysteretic, meaning the charge pump will momentarily turn off until VOUT is sufficiently reduced. The maximum OVP threshold is 6.0V, allowing the use of a ceramic output capacitor rated at 6.3V with no fear of over-voltage damage.
Shutdown State
The device is disabled when the EN pin is low. All registers are reset to default condition when EN is low.
14
SC624A
Applications Information (continued)
Over-Temperature Protection The Over-Temperature (OT) protection circuit helps prevent the device from overheating and experiencing a catastrophic failure. When the junction temperature exceeds 160C, the device goes into thermal shutdown with all outputs disabled until the junction temperature is reduced. All register information is retained during thermal shutdown. Charge Pump Output Current Limit The device also limits the charge pump current at the VOUT pin (typically 300mA). LDO Current Limit The device limits the output currents of LDO1 and LDO2 to help prevent it from overheating and to protect the loads. The minimum limit is 200mA, so load current greater than the rated 100mA can be used with degraded accuracy and larger dropout without tripping the current limit. LED Float Detection Float detect is a fault detection feature of the LED current sink outputs. If an output is programmed to be enabled and an open circuit fault occurs at any current sink output, that output will be disabled to prevent a sustained output OVP condition from occurring due to the resulting open loop. Float detect ensures device protection but does not ensure optimum performance. Unused LED outputs must be disabled to prevent an open circuit fault from occurring.
15
SC624A
Applications Information (continued)
PCB Layout Considerations
The layout diagram in Figure 1 illustrates a proper two-layer PCB layout for the SC624A and supporting components. Following fundamental layout rules is critical for achieving the performance specified in the Electrical Characteristics table. The following guidelines are recommended when developing a PCB layout:
* *
* *
*
Place all bypass and decoupling capacitors -- C1, C2, CIN, COUT, CLDO1, CLDO2, and CBYP as close to the device as possible. All charge pump current passes through VIN, VOUT, and the bucket capacitor connection pins. Ensure that all connections to these pins make use of wide traces so that the resistive drop on each connection is minimized. The thermal pad should be connected to the ground plane using multiple vias to ensure proper thermal connection for optimal heat transfer.
*
*
Make all ground connections to a solid ground plane as shown in the example layout (Figure 3). If a ground layer is not feasible, the following groupings should be connected: PGND -- CIN, COUT AGND -- Ground Pad, CLDO1, CLDO2, CBYP If no ground plane is available, PGND and AGND should be routed back to the negative battery terminal as separate signals using thick traces. Joining the two ground returns at the terminal prevents large pulsed return currents from mixing with the low-noise return currents of the LDOs. Both LDO output traces should be made as wide as possible to minimize resistive losses.
GND
CIN
C1
C2
VOUT
C1+
C2+
VOUT
COUT
CLDO1
LDO1
VIN
C2-
GND
VIN
C1-
PGND
LDO2
CLDO2
Figure 2 -- Layer 1
NC
SC624A
BYP
BL1
EN
CBYP
BL2 SDA
AGND
BL3
BL4
SCL
Figure 1 -- Recommended PCB Layout
NC
Figure 3 -- Layer 2
16
SC624A
Register Map
Address D7 D6 D5 D4 D3 D2 D1 D0 Reset Value
0x00
Description
Backlight Current Control Backlight Enable Control LDO Control
0x00
FADE_1
FADE_0
FADE_EN
BL_4
BL_3
BL_2
BL_1
BL_0
0x01 0x03
0(1) 0(1)
0(1) LDO2_2
0(1) LDO2_1
0(1) LDO2_0
BLEN_4 LDO1_3
BLEN_3 LDO1_2
BLEN_2 LDO1_1
BLEN_1 LDO1_0
0x00 0x00
Note: (1) 0 = always write a 0 to these bits
Register and Bit Definitions (continued)
Backlight Current Control Register (0x00)
This register is used to set the currents for the backlight current sinks, as well as to enable and set the fade step rate. These current sinks need to be enabled in the Backlight Enable Control register to be active. FADE[1:0] These bits are used to set the rise/fall rate between two backlight currents as follows:
FADE_1
0 0 1 1
FADE_0
0 1 0 1
Fade Feature Rise/Fall Rate (ms/step)
32 24 16 8
operation may be cancelled by resetting the fade bit. Clearing the fade bit during an ongoing fade operation changes the backlight current immediately to the value of BL[4:0]. The number of counts to complete a fade operation equals the difference between the old and new backlight values to increment or decrement the BL[4:0] bits. If the fade bit is cleared, the current level will change immediately without the fade delay. The rate of fade may be changed dynamically, even while a fade operation is active, by writing new values to the FADE_1 and FADE_0 bits. The total fade time is determined by the number of steps between old and new backlight values, multiplied by the rate of fade in ms/step. The longest elapsed time for a full scale fade-out of the backlight is nominally 1.024 seconds when the default interval of 32ms is used.
The number of steps in changing the backlight current will be equal to the change in binary count of bits BL[4:0]. FADE_EN This bit is used to enable or disable the fade feature. When the fade function is enabled and a new backlight current is set, the backlight current will change from its current value to a new value set by bits BL[4:0] at a rate of 8ms to 32ms per step. A new backlight level cannot be written during an ongoing fade operation, but an ongoing fade
17
SC624A
Register and Bit Definitions (continued)
BL[4:0] These bits are used to set the current for the backlight current sinks. All enabled backlight current sinks will sink the same current, as shown in Table 1. Table 1 -- Backlight Current Control Bits
BL_4 BL_3 BL_2 BL_1 BL_0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
BL Enable Control Register (0x01)
This register is used to enable the backlight current sinks. BLEN[4:1] These bits are used to enable current sinks (active high, default low). BLEN_4 -- Enable bit for backlight BL4 BLEN_3 -- Enable bit for backlight BL3 BLEN_2 -- Enable bit for backlight BL2 BLEN_1 -- Enable bit for backlight BL1 When enabled, the current sinks will carry the current set by the backlight current control bits BL[4:0], as shown in Table 1.
Backlight Current (mA)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 13 14 15 17 19 21 23 25
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SC624A
Register and Bit Definitions (continued)
LDO Control Register (0x03) This register is used to enable the LDOs and to set their output voltages.
LDO1_3
Table 3 -- LDO1 Control Bits
LDO1_2
0 0 0 0 1 1 1 1 0 0
LDO1_1
0 0 1 1 0 0 1 1 0 0
LDO1_0
0 1 0 1 0 1 0 1 0 1
LDO2[2:0] These bits are used to set the output voltage of LDO2, as shown in Table 2. Table 2 -- LDO2 Control Bits
LDO1 Output Voltage
OFF 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V OFF
0 0 0
LDO2_2
0 0 0 0 1
LDO2_1
0 0 1 1 0
LDO2_0
0 1 0 1 0
LDO2 Output Voltage
OFF 1.8V 1.7V 1.6V 1.5V OFF
0 0 0 0 0 1 1
101 through 111 are not used
LDO1[3:0] These bits set the output voltage of LDO1, as shown in Table 3.
1010 through 1111 are not used
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SC624A
Serial Interface
The I2C General Specification
The SC624A is a read-write slave-mode I C device and complies with the Philips I2C standard Version 2.1, dated January 2000. The SC624A has four user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, supporting direct format for write operation. Read operations are supported on both combined format and stop separated format. While there is no auto increment/decrement capability in the SC624A I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary.
2
by an eighth bit indicating a write. The SC624A I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. Combined Format -- Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC624A I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8 bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. Stop Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC624A then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC624A with a read command. The device acknowledges this request and returns the data from the register location that had previously been set up.
SC624A Limitations to the I2C Specifications
The SC624A only recognizes seven bit addressing. This means that ten bit addressing and CBUS communication are not compatible. The device can operate in either standard mode (100kbit/s) or fast mode (400kbit/s).
Slave Address Assignment
The seven bit slave address is 0110 111x. The eighth bit is the data direction bit. 0x6E is used for a write operation, and 0x6F is used for a read operation.
Supported Formats
The supported formats are described in the following subsections. Direct Format -- Write The simplest format for an I2C write is direct format. After the start condition [S], the slave address is sent, followed
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SC624A
Serial Interface (continued)
I2C Direct Format Write
S Slave Address W A Register Address A Data A P
S - Start Condition W - Write = `0' A - Acknowledge (sent by slave) P - Stop condition
Slave Address - 7-bit Register address - 8-bit Data - 8-bit
I2C Stop Separated Format Read
Register Address Setup Access S Slave Address W A Register Address A P S
S - Start Condition W - Write = `0' R - Read = `1' A - Acknowledge (sent by slave) NAK - Non-Acknowledge (sent by master) Sr - Repeated Start condition P - Stop condition
Master Addresses other Slaves Slave Address B S/Sr
Register Read Access Slave Address RA Data NACK P
Slave Address - 7-bit Register address - 8-bit Data - 8-bit
I2C Combined Format Read
S Slave Address WA Register Address A Sr Slave Address R A Data NACK P
S - Start Condition W - Write = `0' R - Read = `1' A - Acknowledge (sent by slave) NAK - Non-Acknowledge (sent by master) Sr - Repeated Start condition P - Stop condition
Slave Address - 7-bit Register address - 8-bit Data - 8-bit
21
SC624A
Outline Drawing -- MLPQ-UT-20 3x3
A D B
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b D D1 E E1 e L N aaa bbb .020 .000 .024 .002 0.50 0.00 0.60 0.05 (.006) .006 .008 .010 .114 .118 .122 .061 .067 .071 .114 .118 .122 .061 .067 .071 .016 BSC .012 .016 .020 20 .003 .004 (0.1524) 0.15 0.20 0.25 2.90 3.00 3.10 1.55 1.70 1.80 2.90 3.00 3.10 1.55 1.70 1.80 0.40 BSC 0.30 0.40 0.50 20 0.08 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 e LxN E/2 E1
2 1 N
SEATING PLANE C D1
D/2 bxN bbb
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
CAB
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS . 3. DAP is 1.90 x 190mm.
22
SC624A
Land Pattern -- MLPQ-UT-20 3x3
H R DIM C G H K P R X Y Z DIMENSIONS INCHES (.114) .083 .067 .067 .016 .004 .008 .031 .146 MILLIMETERS (2.90) 2.10 1.70 1.70 0.40 0.10 0.20 0.80 3.70
(C)
K
G
Z
Y X P NOTES: 1. 2.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
3.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com
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